Noise-Biased Surface Code Thresholds Under Realistic Gate Sets
We evaluate thresholds for the surface code under biased noise models using realistic gate decompositions and circuit scheduling. We compare analytical bounds with Monte Carlo simulations and quantify logical error rates across code distances.
Problem Workspace
Problem Statement
Study the surface code under noise models with dephasing bias (Z-dominant) and gate-dependent error rates. Derive expected threshold behavior from literature and implement simulations to estimate logical error rates for distances d ∈ {3,5,7,9}. Use Qiskit Aer (or Stim if available) to build circuits for repeated syndrome extraction with lattice surgery style checks. For each bias ratio η ∈ {1, 5, 20, 50} and physical error p ∈ [1e-4, 5e-2], estimate logical error per round and fit threshold curves. Compare against theoretical predictions and prior SOTA results; document limitations and mismatches.
Execution plan
No evaluation plan has been provided for this problem yet.